Huawei presented the Tau (τ) Scaling Law- a new principle for guiding the future development of the semiconductor industry

Today, at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS), Huawei’s He Tingbo delivered a keynote speech titled “New Semiconductor Path in Practice.” In this speech, she presented the Tau (τ) Scaling Law.

HUAWEI has presented the Tau (τ) Scaling Law, a new principle for guiding the future development of the semiconductor industry. By 2031, HUAWEI's high-end chips based on this law are expected to feature a transistor density that is equivalent to 14 Å (1.4 nm) processes.

— Huawei (@Huawei) May 25, 2026

Huawei’s Tau (τ) Scaling Law

This law is a new principle for guiding the future development of the semiconductor industry. This law proposes replacing geometric scaling with time (τ) scaling as a new guiding principle for the evolution of both semiconductors and electronic systems.

It is further explained that, based on this principle, innovative technologies such as LogicFolding can be used to continuously compress signal propagation delay and steadily improve transistor density, which will drive the ongoing evolution of semiconductors and electronic systems.

Previously, Moore’s law guided the semiconductor industry for more than five decades, but it is said to face severe physical limits and diminishing economic returns. To match the surging computing demands, this new Tau (τ) Scaling law is presented by the brand.

It is revealed that based on this law, Huawei has developed innovative core technologies like LogicFolding and established a multi-level co-optimisation mechanism that spans semiconductor devices, circuits, chips and systems.

This mechanism aims to shorten the time constraint (τ) in the following ways:

• At the device level: Optimizing the resistance and parasitic capacitance of transistors and interconnects to minimize the device-level time constant τ at the underlying physical layer
• At the circuit level: Adopting the LogicFolding architecture to break down the physical boundaries of traditional circuit layouts, significantly shortening critical-path wiring, effectively reducing the resistive and capacitive load of signal propagation, and ultimately boosting transistor density and circuit performance
• At the chip level: Employing full-stack coordinated design of software, architecture, and silicon to achieve fine-grained, workload-driven control over instruction and data flows, enhancing system-level parallelism and efficiency, and significantly reducing end-to-end execution time
• At the system level: Redefining interconnect protocols for computing systems with UnifiedBus to achieve unified memory addressing and native memory semantics for SuperPoDs, significantly reducing system communications latency

In the past six years, Huawei has designed and mass-produced 381 chips based on this new law. It is shared that the Kirin chips that are scheduled to launch in Fall 2026 will be the first ever to adopt the LogicFolding architecture, which will considerably enhance the chip performance. Also by 2031, the high-end chips HUAWEI designs based on the τ Scaling Law are expected to feature a transistor density that is equivalent to 14 A (1.4 nm) processes.

With this new law, Huawei is looking forward to working closely with scientists, engineers, and industry partners around the world to drive the sustainable development of the semiconductor and electronics industries.